Both analog and digital phase lock loop circuitry are well known in the electronics art. Analog phase lock loops require frequent adjustment and calibration which are expensive in terms of both time and money. In addition, analog phase lock loops sometimes have stability problems. Attempts to minimize these problems have often resulted in an excessive cost for the phase lock loop portion of a circuit. In addition, many controllers for a flexible disk memory system are digital and require maintenance people having digital experience. A digital phase lock loop can capitalize on this digital experience and eliminate a need for maintenance people having analog circuitry expertise.
Conventional digital phase lock loop systems require the positioning of a fixed duration window about either data bits or clock bits. Positioning of such a window does not compensate for variations in flexible disk rotation rates, thereby resulting in a bit window having a duration which covers a variable percentage of the time interval allocated to each data or clock bit. In addition, conventional systems position a fixed duration window with respect only to the position of a single bit relative to its corresponding window. A disadvantage of this technique is the creation of a window having considerable jitter if pulses are almost centered but occur first on one side and then on the other side of a central position. The phase lock loop system of the present invention eliminates the above problems.